1. Field
Embodiments described herein relate generally to a BIST circuit.
2. Background Art
In a conventional method, a built-in self-test circuit (hereinafter, will be called a BIST circuit) is incorporated into a memory device built in a semiconductor integrated circuit and a failure is detected during a manufacturing test.
Failure detecting methods includes a comparator BIST in which written data and read data are compared with each other to decide the presence or absence of failures and a compressor BIST in which read results are compressed in a BIST circuit and the presence or absence of failures is decided based on the compressed results.
If a test sequence is generated with a complicated address transition in such a conventional BIST circuit, a circuit configuration for generating the test sequence needs to be more complicated.